The embodiments of the invention generally relate to integrated circuit devices and, more particularly, to an improved integrated circuit switching device with merged field effect transistor (FET) cells for minimized series resistance as well as minimized parasitic capacitance in order to avoid signal frequency losses.
Numerous integrated circuit applications require switching. Most integrated circuit switching devices (i.e., switches) are implemented with one or more field effect transistors (FETs). A simple FET switch functions by selectively applying a voltage on the FET in order to create a low resistance signal path in the FET channel region between the FET drain and source regions. However, losses in the frequency of this signal as it passes through the channel region can occur due to a number of different factors. For example, parasitic capacitance between the wafer substrate and the drain region, source region and channel region of the FET can cause such a frequency loss. As the frequency of the signal increases, loss due such parasitic capacitances also increases. Series resistance in the FET wiring is also a factor. Furthermore, if multiple FETs are incorporated into a single switching device, such parasitics become an even greater factor in signal frequency losses.
Therefore, there is a need in the art form an improved integrated circuit switching device having minimized series resistance as well as minimized parasitic capacitance in order to avoid signal frequency losses.